I. Field of the Disclosure
The technology of the disclosure relates generally to static random access memories (SRAM) with improved performance characteristics.
II. Background
Mobile communication devices have become common in current society. The prevalence of these mobile devices is driven in part by the many functions that are now enabled on such devices. Demand for such functions increases processing capability requirements and generates a need for more powerful batteries. Within the limited space of the housing of the mobile communication device, batteries compete with the processing circuitry. These and other factors contribute to a continued miniaturization of components within the circuitry.
Miniaturization of the components impacts all aspects of the processing circuitry including the memory transistors and other reactive elements in the processing circuitry. While miniaturization of components in mobile communication devices is easy for the consumer to appreciate as phones become smaller and lighter and have longer battery times, miniaturization pressures are not limited to mobile communication devices. Computing devices ranging from mobile communication devices to desktop computers to servers and the like all benefit from miniaturization efforts. In particular, almost all of these devices have various forms of memory such as dynamic random access memory (DRAM) and static random access memory (SRAM).
A basic SRAM bit cell structure relics on six transistors that form two cross-coupled inverters that store each memory bit. A typical SRAM uses metal oxide field effect transistors (MOSFETs) for each of the six transistors. The smaller the transistors, the more transistors may be placed in a given amount of space in a memory chip and the more memory that the memory chip can provide.
As SRAM is miniaturized to the twenty-two nanometer (22 nm) scale and smaller, the geometries associated with these reduced scales preclude compliance with a 6σ yield. That is, the 6σ standard requires that 99.99966% of the devices are free from defects and meet the design criteria. In particular, SRAM designers have defined a number of parameters, including three noise parameters (e.g., Static Noise Margin (SNM), Hold Static Noise Margin (HSNM), and Write Ability Margin (WAM)) and the basic six transistor (6T) design fails to meet 6σ in both the SNM and the WAM parameters. Accordingly, there is a desire amongst memory designers to improve the SNM and WAM parameters of SRAM bit cells.